Xilinx 7 Series User Manual page 41

The switching condition for BUFGCE is similar to BUFGCTRL. If the CE input is Low prior
to the incoming rising clock edge, the following clock pulse does not pass through the
clock buffer, and the output stays Low. Any level change of CE during the incoming clock
High pulse has no effect until the clock transitions Low. The output stays Low when the
clock is disabled. However, when the clock is being disabled it completes the clock High
pulse.
Since the clock enable line uses the CE pin of the BUFGCTRL, the select signal must meet
the setup time requirement. Violating this setup time can result in a glitch.
illustrates the timing diagram for BUFGCE.
X-Ref Target - Figure 2-8
BUFGCE_1 is similar to BUFGCE, with the exception of its switching condition. If the CE
input is Low prior to the incoming falling clock edge, the following clock pulse does not
pass through the clock buffer, and the output stays High. Any level change of CE during
the incoming clock Low pulse has no effect until the clock transitions High. The output
stays High when the clock is disabled. However, when the clock is being disabled it
completes the clock Low pulse.
Figure 2-9
X-Ref Target - Figure 2-9
BUFGMUX and BUFGMUX_1
BUFGMUX is a clock buffer with two clock inputs, one clock output, and a select line. This
primitive is based on BUFGCTRL with some pins connected to logic High or Low.
Figure 2-10
is available for manually placing the BUFGMUX and BUFGCTRL locations. See the
Constraints Guide for more information.
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
BUFGCE(I)
BUFGCE(CE)
BUFGCE(O)
Figure 2-8: BUFGCE Timing Diagram
illustrates the timing diagram for BUFGCE_1.
BUFGCE_1(I)
BUFGCE_1(CE)
BUFGCE_1(O)
Figure 2-9: BUFGCE_1 Timing Diagram
illustrates the relationship of BUFGMUX and BUFGCTRL. The LOC constraint
www.xilinx.com
Global Clocking Resources
T
BCCCK_CE
T
BCCKO_O
T
BCCCK_CE
T
BCCKO_O
Figure 2-8
UG472_c1_08_061310
UG472_c1_09_061310
41