Mmcm Attributes - Xilinx 7 Series User Manual

CLKINSTOPPED – Input Clock Status
Status pin indicating that the input clock has stopped. This signal is asserted within one
clock cycle of clock stoppage. The signal is deasserted after the clock has restarted and
LOCKED is achieved or the clock is switched to the alternate clock input and the MMCM
has re-locked. Not available in the PLL.
CLKFBSTOPPED – Feedback Clock Status
Status pin indicating that the feedback clock has stopped. This signal is asserted within one
clock cycle of clock stoppage. The signal is deasserted after the feedback clock has restarted
and the MMCM has re-locked. Not available in the PLL.
LOCKED
An output from the MMCM/PLL used to indicate when the MMCM/PLL have achieved
phase and frequency alignment of the reference clock and the feedback clock at the input
pins. Phase alignment is within a predefined window and frequency matching within a
predefined PPM range. The MMCM automatically locks after power on, no extra reset is
required. LOCKED will be deasserted within one clock cycle if the input clock stops, the
phase alignment is violated (e.g., input clock phase shift) or the frequency has changed.
The MMCM/PLL must be reset when LOCKED is deasserted. The clock outputs should
not be used prior to the assertion of LOCKED.
DO[15:0] – Dynamic Reconfiguration Output Bus
The dynamic reconfiguration output bus provides MMCM data output when using
dynamic reconfiguration. If DWE is inactive while DEN is active at the rising edge of
DCLK, then this bus holds the content of the configuration cells addressed by DADDR.
The DO bus must be captured on the rising edge of DCLK when DRDY is active. The DO
bus value is held until the next DRP operation.
DRDY – Dynamic Reconfiguration Ready
The dynamic reconfiguration ready output (DRDY) provides the response to the DEN
signal for the MMCMs dynamic reconfiguration feature. This signal indicates that a DEN/
DCLK operation has completed.
PSDONE – Phase Shift Done
The phase-shift done output signal is synchronous to the PSCLK. When the current
phase-shift operation is completed, the PSDONE signal is asserted for one clock cycle
indicating that a new phase-shift cycle can be initiated. Not available in the PLL.

MMCM Attributes

Table 3-7
Table 3-7: MMCM Attributes
Attribute
BANDWIDTH
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
lists the attributes for the MMCME2_BASE and MMCME2_ADV primitives.
Type Allowed Values
String HIGH
LOW
OPTIMIZED
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General Usage Description
Default
OPTIMIZED Specifies the MMCM
programming algorithm affecting
the jitter, phase margin and other
characteristics of the MMCM.
Description
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