Mmcme2_Adv And Plle2_Adv Primitive - Xilinx 7 Series User Manual

The PLLE2_BASE primitive provides access to the most frequently used features of a stand
alone PLL. Clock deskew, frequency synthesis, coarse phase shifting, and duty cycle
programming are available to use with the PLLE2_BASE. The ports are listed in
Table 3-2: PLLE2_BASE Ports

MMCME2_ADV and PLLE2_ADV Primitive

The MMCME2_ADV primitive provides access to all MMCME2_BASE features plus
additional ports for clock switching, access to the
well as dynamic fine-phase shifting. The ports are listed in
Table 3-3: MMCME2_ADV Ports
The PLLE2_ADV primitive provides access to all PLLE2_BASE features plus additional
ports for clock switching, and access to the
listed in
Table 3-4: PLLE2_ADV Ports
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7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Description
Clock Input
Control Inputs
Clock Output
Status and Data Outputs
Description
Clock Input
Control and Data Input
Clock Output
Status and Data Output
Power Control
Table 3-4.
Description
Clock Input
Control and Data Input
Clock Output
Status and Data Output
Power Control
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CLKIN1, CLKFBIN
RST
CLKOUT0 to CLKOUT5, CLKFBOUT
LOCKED
Dynamic Reconfiguration Port
CLKIN1, CLKIN2, CLKFBIN, DCLK, PSCLK
RST, CLKINSEL, DWE, DEN, DADDR, DI, PSINCDEC, PSEN
CLKOUT0 to CLKOUT6, CLKOUT0B to CLKOUT3B,
CLKFBOUT, and CLKFBOUTB
LOCKED, DO, DRDY, PSDONE, CLKINSTOPPED,
CLKFBSTOPPED
PWRDWN
Dynamic Reconfiguration
CLKIN1, CLKIN2, CLKFBIN, DCLK
RST, CLKINSEL, DWE, DEN, DADDR, DI
CLKOUT0 to CLKOUT5, and CLKFBOUT
LOCKED, DO, DRDY
PWRDWN
General Usage Description
Port
Table 3-3.
Ports
Port. The ports are
Port
Table 3-2.
(DRP), as
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