Clocking Differences In 7 Series Fpgas - Xilinx 7 Series User Manual

Clocking Differences in 7 Series FPGAs

Each of the 7 series FPGA families have some unique connectivity requirements.
lists the connectivity limitations described in
comprehensive graphical representation of the GT, CMT, and I/O locations and
alignments, see the Die Level Bank Numbering Overview section in UG475, 7 Series FPGA
Packaging and Pinout Specification.
Table 1-2: Clocking Connectivity Differences by 7 Series FPGAs
www.BDTIC.com/XILINX
7 Series FPGAs Clocking Resources User Guide
UG472 (v1.5) July 13, 2012
Family
Artix-7 FPGAs: There are no direct connections from the GTP transceivers to the
CMTs and BUFMRs. When connecting from the GTP transceivers to
XC7A100T, XC7A200T,
a CMT, a BUFH or BUFG is required.
and XC7A350T
There are no direct connections from the GTX transceivers to the
Kintex-7 FPGAs:
CMTs and BUFMRs. When connecting from the GTX transceivers to
All devices
a CMT, a BUFH or BUFG is required.
There are no connectivity exceptions. See
All Virtex-7 T and XT Interconnect Clocking in Chapter 2
FPGAs designing with the XC7V1500T, XC7V2000T, and XC7VX1140T
devices.
GTZ transceivers can only connect to the interposer clock backbone
to connect to SLRs. Thus, they can only drive global clock networks
All Virtex-7 HT FPGAs
(BUFG routing tracks) and BUFHs and can only be driven by
BUFGs. See
www.xilinx.com
Summary of Clock Connectivity
Table 1-1 by device family. For a
Exceptions
for clocking guidelines when
Stacked Silicon Interconnect Clocking in Chapter
Table 1-2
Stacked Silicon
2.
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