Bridge Parameters - Xilinx LogiCORE IP AXI Product Manual

Table 2-3: Top-Level Interface Signals (Cont'd)
Signal Name
s_axi_ctl_rvalid
s_axi_ctl_rready
intx_msi_request
intx_msi_grant
msi_enable
msi_vector_num [4:0]
msi_vector_width [2:0]
pci_exp_rxp[c_no_of_lanes-1: 0]
pci_exp_rxn[c_no_of_lanes-1: 0]
pci_exp_txp[c_no_of_lanes-1: 0]
pci_exp_txn[c_no_of_lanes-1:0]

Bridge Parameters

Because many features in the AXI Bridge for PCI Express core design can be parameterized,
you are able to uniquely tailor the implementation of the core using only the resources
required for the desired functionality. This approach also achieves the best possible
performance with the lowest resource usage.
The parameters defined for the AXI Bridge for PCI Express are shown in
Table 2-4: Top-Level Parameters
Generic Parameter Name
C_PCIE_BLK_LOCN
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
I/O Description
O Slave read valid
I Slave read ready
MSI Signals
Legacy interrupt input (see c_interrupt_pin) when
msi_enable = 0.
I
Initiates a MSI write request when msi_enable = 1.
Intx_msi_request is asserted for one clock period.
Indicates legacy interrupt/MSI grant signal. The
O intx_msi_grant signal is asserted for one clock period
when the interrupt is accepted by the PCIe core.
O Indicates when MSI is enabled.
Indicates MSI vector to send when writing a MSI write
I
request.
Indicates the size of the MSI field (the number of MSI
O
vectors allocated to the device).
PCIe Interface
I PCIe RX serial interface
I PCIe RX serial interface
O PCIe TX serial interface
O PCIe TX serial interface
Description
Bridge Parameters
0: X0Y0
1: X0Y1
PCIe integrated
block location 2: X0Y2
within FPGA
3: X1Y0
4: X1Y1
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Chapter 2: Product Specification
Allowable Values Default Value VHDL Type
Table 2-4.
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