Chapter 1: Overview; Dsp48E1 Slice Overview - Xilinx 7 Series User Manual

Overview

DSP48E1 Slice Overview

FPGAs are efficient for digital signal processing (DSP) applications because they can
implement custom, fully parallel algorithms. DSP applications use many binary
multipliers and accumulators that are best implemented in dedicated DSP slices. All
7 series FPGAs have many dedicated, full-custom, low-power DSP slices, combining high
speed with small size while retaining system design flexibility. The DSP slices enhance the
speed and efficiency of many applications beyond digital signal processing, such as wide
dynamic bus shifters, memory address generators, wide bus multiplexers, and
memory-mapped I/O registers. The basic functionality of the DSP48E1 slice is shown in
Figure
and
X-Ref Target - Figure 1-1
B
A
D
C
Some highlights of the DSP functionality include:
•
•
•
7 Series DSP48E1 User Guide
UG479 (v1.10) March 27, 2018
1-1. For complete details, refer to
Specifics.
+ / –
Pre-adder
Figure 1-1: Basic DSP48E1 Slice Functionality
25 × 18 two's-complement multiplier:
• Dynamic bypass
48-bit accumulator:
• Can be used as a synchronous up/down counter
Power saving pre-adder:
• Optimizes symmetrical filter applications and reduces DSP slice requirements
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Figure 2-1 and Chapter 2, DSP48E1 Description
48-Bit Accumulator/Logic Unit
+
X
–
25 x 18
Multiplier
=
Pattern Detector
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