Siemens Simovert Masterdrives Compendium page 971

U950.22 = ___(20)
Only allowed for PWE 2 or 20 (inactive).
Fine synchronization
SIMOLINK
Fine synchronization can cause a smaller
synchronization deviation (r748.9).
Fine synchronization has a greater effect the
higher the bus cycle time (P746)/T2 ratio.
(with Transceiver)
1 2
SIMOLINK board (SLB)
Synchronizing
Maximum
synchronized
time slot
SIMOLINK
0...10
P754 (0)
cycle time
Sync time counter
P753 (0)
K
Synchroniz ing conditions :
( )
= =
P 754 0 : Cycle time P 746
Pulse
( )
≠ =
P 754 : 0 Cycle time P 746
Pulse
3
Setting of P755:
Dead time compensation:
xxx0: No dead time compensation.
xxx1: Compensation of different dead times between units.
SLB switchover (between 2 SLBs):
xx0x: Switchover in operation disabled.
xx1x: Switchover in operation enabled.
Bus cycle time:
x0xx: Bus cycle time is corrected internally over all telegrams.
x1xx: Bus cycle time is exactly implemented.
[420.5]
SIMOLINK
Pulse frequency
[140.1]
configuration
0000 ... 1111
P755 (0)
Synchronizing
PLL
⎛ =
1 n largest synchroniz
⎜
⋅ n
( ) 2
⎜
≥
frequency P 340 ⎝ n 2
⎛ =
m smallest synchroniz
⎜
1
⋅ m ≥
⎜
( ) 2 m 2
⎜
frequency P 340
=
P 754 largest synchroniz
⎝
4 5
V2.5
1
Alarm A003 "not synchronous"
B0043 Drive in synchronism
Time counter
K0260 (Dispatcher only)
⎞
ed time slot
⎟
⎟
⎠
⎞
ed time slot
⎟
⎟
⎟
ed time slot
⎠
6 7
Function diagram
fp_mc_141_e.vsd
MASTERDRIVES MC
23.10.02
n959.22 = 4
8
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