Single-Slot Parallel Smbus Circuit; Pull-Ups/Pull-Downs In Single-Slot Parallel Mode; Reference Schematic For Single-Slot Parallel Mode - Intel Pentium M Processor Design Manual

® ®
Intel Pentium M Processor and Intel
®
Intel 82870P2 (Intel P64H2)
ready for it to become deasserted. Pull the PAGNT4 (HxBUSENB#) signal to 3.3 V through a 10
kΩ ± 5% resistor. The Intel
must be asserted.
8.2.7.8

Single-Slot Parallel SMBus Circuit

Figure 98
Figure 98.

Single-Slot Parallel SMBus Circuit

NOTE: The pin names shown in the Intel
mode, refer to
8.2.7.9

Pull-Ups/Pull-Downs in Single-Slot Parallel Mode

All PCI signals should follow the PCI Local Bus Specification, Revision 2.2, pull-up requirements
whether they are multiplexed or not. All unused input signals should be pulled to 3.3 V through an
8.2 kΩ ± 5% resistor to keep them from floating.
Table 76
whether in single or dual-slot parallel mode, all signals from
even though only the signals listed in
in Table 76
8.2.7.10

Reference Schematic for Single-Slot Parallel Mode

Note that the schematic in
schematic has not been fully validated.
140
®
E7501 Chipset Platform
®
P64H2 may be able to drive this signal to ground when the signal
shows the single-slot parallel SMBus circuit.
HX_RESETA#
®
Intel
P64H2
HX_BUSENB#
Table 76 for the corresponding Intel P64H2 pin name.
defines which multiplexed signals are to be used with single-slot parallel mode. Note that
must be pulled to 3.3 V through an 8.2 kΩ ± 5% resistor to keep them from toggling.
Figure 99
3.3V
100 kΩ
®
P64H2 block are hot-plug slot signal names. For single-slot parallel
Table 76
Table 77 are used. As a result, all unused input signals listed
is based on definition and simulation of the Intel
10 kΩ
Slot 1
are actually multiplexed
®
P64H2. The
Design Guide