General Guidelines; Termination Resistors - Intel EP80579 Manual

26.2.4

General Guidelines

For some signals, the existence of on-die termination (ODT) within the processor or
chipset will remove parts from the platform design. The processor or chipset-specific
Thermal Design Specification will clarify if ODT exists on signals for this guideline.
Electrical lengths are provided in units of flight time. Conversion of flight time to board-
trace lengths is dependent on what layer routing occurs on and the dielectric constant
of the board materials for a specific design. Rule-of-thumb numbers can be derived by
using 140 to 180ps/inch for outer layers of an FR4 product and 180ps/inch for inner
layers.
Signals must be routed using 45 to 65 ohm +/-10% impedance traces. The length of
any unterminated stub on any TCK (1:0) or observation-port pin nets must be less than
200ps unless otherwise stated. The 51 +/- 5% ohm recommendation in this document
for signal termination has been proven to work on all recommended board impedances.
JTAG and observation-port signals my optionally be terminated using the nominal-
board impedance.
Debug port signals that are not discussed within this document may be assumed to be
left floating, thus no termination is required.
TCK1, TCK0, system clocks, and all of the observation pins should be routed with high-
speed design rules in mind, in particular:
• An effort should be made to minimize the number of layer transitions and plane
split crossings imposed on each trace (ideally this will be zero). If return paths are
well kept then the number of vias are nearly immaterial.
• Keep the critical signals referenced to GND whenever possible.
• Include ground-stitching vias near every layer transition. This is important even
when referencing the same voltage on the new layer because the stitching via may
reduce return current loops on the trace.
• For situations where these signals are routed referenced to one or more power
planes, include a bypass capacitor near every layer transition or plane split
between the two referenced planes.
• An effort should be made not to share XDP bypass capacitors with other high-speed
signals.
• For all signals, pull-up termination resistors should be located above a solid-power
plane. If a solid-power plane does not exist at the required termination location,
add a 0.1uF ceramic capacitor to GND on the pull-up voltage within 0.5 inches of
termination resistor.
26.2.5

Termination Resistors

Termination resistances are given, with tolerances, whenever appropriate. Tolerances
are within +/- of the percentage.
With few exceptions (noted specifically in their description), termination resistors must
be close to the receiver. The topology, at the end of the chain, must be terminated in
one of the following ways (in all cases) except those noted in their specific description.
In the case of
be smaller than any noted maximum routing length. This is the typical way of showing
terminations in this document. There is no restriction for the length of (B) unless
otherwise noted.
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Intel EP80579 Integrated Processor Product Line
Platform Design Guide
260
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Intel EP80579 Integrated Processor Product Line—Debug Port Design Guide
Figure 153, where there is a termination after the last receiver, (A) must
May 2010
Order Number: 320068-005US