Relative Timings - Intel 80C186EC Manual

AC Characteristics 80L186EC16
NOTES
1 See AC Timing Waveforms for waveforms and definition
2 Measure at V for high time V
IH
3 Only required to guarantee I
4 Specified for a 50 pF load see Figure 14 for capacitive derating information
5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF
6 See Figure 15 for rise and fall times
7 T applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release
CHOV1
8 T applies to RD and WR only after a HOLD release
CHOV2
9 Setup and Hold are required to guarantee recognition
10 Setup and Hold are required for proper operation
Relative Timings (80C186EC-25 20 13 80L186EC-16 13)
Symbol

RELATIVE TIMINGS

T ALE Active Pulse Width
LHLL
T AD Valid Setup before ALE Falls
AVLL
T Chip Select Valid before ALE Falls
PLLL
T AD Hold after ALE Falls
LLAX
T ALE Falling to WR Falling
LLWL
T ALE Falling to RD Falling
LLRL
T WR Rising to Next ALE Rising
WHLH
T AD Float to RD Falling
AFRL
T RD Active Pulse Width
RLRH
T WR Active Pulse Width
WLWH
T RD Rising to Next Address Active
RHAX
T Output Data Hold after WR Rising
WHDX
T WR Rise to Chip Select Rise
WHPH
T RD Rise to Chip Select Rise
RHPH
T Chip Select Inactive to Next Chip
PHPL
Select Active
T ONCE Active Setup to RESIN Rising
OVRH
T ONCE Hold after RESIN Rise
RHOX
T INTA High to Next INTA Low
IHIL
during INTA Cycle
T INTA Active Pulse Width
ILIH
T CAS2 0 Setup before 2nd INTA
CVIL
Pulse Low
T CAS2 0 Hold after 2nd INTA Pulse Low
ILCX
T Interrupt Resolution Time
IRES
T IR Low Time to Reset Edge Detector
IRLH
T IR Hold Time after 1st INTA Falling
IRHIF
(Continued)
for low time
IL
Maximum limits are bounded by T
CC
Parameter
80C186EC 188EC 80L186EC 188EC
T and T
C CH CL
Min Max
T 15
b
T 10
b
T 10
b
T 10
b
T 15
b
T 15
b
T 10
b
0
2T 5
b
2T 5
b
T 15
b
T 15
b
T 10
b
T 10
b
T 10
b
T
T
4T 5
b
2T 5
b
8T
4T
150
50
25
Unit Notes
ns
ns
ns 1
ns
ns 1
ns 1
ns 1
ns
ns 2
ns 2
ns
ns
ns 1
ns 1
ns 1
ns
ns
ns 4
ns 2 4
ns 2 4
ns 2 4
ns 3
ns
ns 4 5
35