Double Bus Fault - Motorola CPU32 Reference Manual

7.2.2.3 Double Bus Fault

The CPU32 normally treats a double bus fault, or two bus faults in succession, as a
catastrophic system error, and halts. When this condition occurs during initial system
debug (a fault in the reset logic), further debugging is impossible until the problem is
corrected. In BDM, the fault can be temporarily bypassed, so that its origin can be iso-
lated and eliminated.
7.2.2.4 Peripheral Breakpoints
CPU32 peripheral breakpoints are implemented in the same way as external break-
points — peripherals request breakpoints by asserting the BKPT signal. Consult the
appropriate peripheral user's manual for additional details on the generation of periph-
eral breakpoints.
7.2.3 Entering BDM
When the processor detects a breakpoint or a double bus fault, or decodes a BGND
instruction, it suspends instruction execution and asserts the FREEZE output. This is
the first indication that the processor has entered BDM. Once FREEZE has been as-
serted, the CPU enables the serial communication hardware and awaits a command.
The CPU writes a unique value indicating the source of BDM transition into temporary
register A (ATEMP) as part of the process of entering BDM. A user can poll ATEMP
and determine the source (see Table 7-2) by issuing a read system register command
(RSREG). ATEMP is used in most debugger commands for temporary storage — it is
imperative that the RSREG command be the first command issued after transition into
BDM.
Double Bus Fault
BGND Instruction
Hardware Breakpoint
*Special status word (SSW) is described in detail in 6.3 Fault Recovery.
A double bus fault during initial stack pointer/program counter (SP/PC) fetch sequence
is distinguished by a value of $FFFFFFFF in the current instruction PC. At no other
time will the processor write an odd value into this register.
7.2.4 Command Execution
Figure 7-4 summarizes BDM command execution. Commands consist of one 16-bit
operation word and can include one or more 16-bit extension words. Each incoming
word is read as it is assembled by the serial interface. The microcode routine corre-
sponding to a command is executed as soon as the command is complete. Result op-
erands are loaded into the output shift register to be shifted out as the next command
is read. This process is repeated for each command until the CPU returns to normal
operating mode.
CPU32
REFERENCE MANUAL
Table 7-2 Polling the BDM Entry Source
Source
DEVELOPMENT SUPPORT
ATEMP [31:16]
SSW*
$0000
$0000
ATEMP [15:0]
$FFFF
$0001
$0000
MOTOROLA
7-5