Interrupts - Motorola CPU32 Reference Manual

If an instruction is executed and an interrupt is pending on completion, the trace
exception is processed before the interrupt exception.
If an instruction forces an exception, the forced exception is processed before the
trace exception.
If an instruction is executed and a breakpoint is pending upon completion of the in-
struction, the trace exception is processed before the breakpoint.
If an attempt is made to execute an illegal, unimplemented, or privileged instruction
while tracing is enabled, no trace exception will occur because the instruction is not
executed. This is particularly important to an emulation routine that performs an in-
struction function, adjusts the stacked program counter to beyond the unimple-
mented instruction, and then returns. The status register on the stack must be
checked to determine if tracing is on before the return is executed. If tracing is on,
trace exception processing must be emulated so that the trace exception handler
can account for the emulated instruction.
Tracing also affects normal operation of the STOP and LPSTOP instructions. If either
begins execution with T1 set, a trace exception will be taken after the instruction loads
the status register. Upon return from the trace handler routine, execution will continue
with the instruction following STOP (LPSTOP), and the processor will not enter the
stopped condition.

6.2.11 Interrupts

There are seven levels of interrupt priority and 192 assignable interrupt vectors within
each exception vector table. Judicious use of multiple vector tables and hardware
chaining will permit a virtually unlimited number of peripherals to interrupt the proces-
sor.
Interrupt recognition and subsequent processing are based on internal interrupt re-
quest signals (IRQ7–IRQ1) and the current priority set in status register priority mask
I[2:0]. Interrupt request level zero (IRQ7–IRQ1 negated) indicates that no service is re-
quested. When an interrupt of level one through six is requested via IRQ6–IRQ1, the
processor compares the request level with the interrupt mask to determine whether the
interrupt should be processed. Interrupt requests are inhibited for all priority levels less
than or equal to the current priority. Level seven interrupts are nonmaskable.
IRQ7–IRQ1 are synchronized and debounced by input circuitry on consecutive rising
edges of the processor clock. To be valid, an interrupt request must be held constant
for at least two consecutive clock periods.
Interrupt requests do not force immediate exception processing, but are left pending.
A pending interrupt is detected between instructions or at the end of exception pro-
cessing — all interrupt requests must be held asserted until they are acknowledged by
the CPU. If the priority of the interrupt is greater than the current priority level, excep-
tion processing begins.
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EXCEPTION PROCESSING CPU32
REFERENCE MANUAL