Serial Interface Timing Diagram - Motorola CPU32 Reference Manual

Both DSCLK and DSI are synchronized to on-chip clocks, thereby minimizing the
chance of propagating metastable states into the serial state machine. Data is sam-
pled during the high phase of CLKOUT. At the falling edge of CLKOUT, the sampled
value is made available to internal logic. If there is no synchronization between CPU32
and development system hardware, the minimum hold time on DSI with respect to
DSCLK is one full period of CLKOUT.
CLKOUT
FREEZE
DSCLK
SAMPLE
WINDOW
INTERNAL
SYNCHRONIZED
DSCLK
INTERNAL
SYNCHRONIZED
The serial state machine begins a sequence of events based on the rising edge of the
synchronized DSCLK (see Figure 7-6). Synchronized serial data is transferred to the
input shift register, and the received bit counter is decremented. One-half clock period
later, the output shift register is updated, bringing the next output bit to the DSO signal.
DSO changes relative to the rising edge of DSCLK and does not necessarily remain
stable until the falling edge of DSCLK.
One clock period after the synchronized DSCLK has been seen internally, the updated
counter value is checked. If the counter has reached zero, the receive data latch is up-
dated from the input shift register. At this same time, the output shift register is reload-
ed with the "not ready/come again" response. Once the receive data latch has been
loaded, the CPU is released to act on the new data. Response data overwrites the "not
ready" response when the CPU has completed the current operation.
Data written into the output shift register appears immediately on the DSO signal. In
general, this action changes the state of the signal from a high ("not ready" response
status bit) to a low (valid data status bit) logic level. However, this level change only
occurs if the command completes successfully. Error conditions overwrite the "not
ready" response with the appropriate response that also has the status bit set.
CPU32
REFERENCE MANUAL
DSI
DSI
DSO
Figure 7-6 Serial Interface Timing Diagram
DEVELOPMENT SUPPORT MOTOROLA
7-9