Serial Mode Register (Smr) - Fujitsu F2MC-16LX Hardware Manual

17.3.1 Serial Mode Register (SMR)

The SMR register specifies a UART operating mode.
Set an operating mode when the register is stopping. Do not write anything to the
register during operation.
■ Serial Mode Register (SMR)
Figure 17.3-2 Configuration Of Serial Mode Register (SMR)
Serial mode register
Address:000020
H
Read/write
Initial value
[bit7, bit6] MD1 and MD0 (Mode select)
MD1 and MD0 bits select a UART operating mode.
Table 17.3-1 MD1 and MD0 (Operating Mode Selecting Bits)
MD1
0
0
1
1
Note:
The synchronous mode (multiprocessor) of mode 1 is a mode in which multiple slave CPUs
are connected to one host CPU.
The peripherals are not capable of identifying a receiver data format. Therefore, only the
master multiprocessor mode is supported.
Also, the parity check function is not available, so set the PEN of the SCR register to "0".
[bit5 to bit3] CS2, CS1, and CS0 (Clock select)
CS2 to CS0 bits select a baud rate clock source.
If the communication prescaler is selected, a baud rate is also determined simultaneously.
The bits are initialized to "000" when reset.
7 6 5
bit
MD1 MD0 CS2 CS1
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0)
MD0 Mode
0 0
1 1
0 2
1 -
4 3 2 1
CS0 Reserved SCKE SOE
(0) (0) (0)
Operating mode
Asynchronous (start-stop synchronous)
normal mode [Initial value]
Asynchronous (start-stop synchronous)
multiprocessor mode
CLK-synchronous mode
Do not use
17.3 UART Registers
0
SMR
(0)
261