Serial Mode Register (Smr) - Fujitsu FR60 Hardware Manual

13.2.1 Serial Mode Register (SMR)

The serial mode register (SMR) specifies the UART operating mode.
Set an operating mode while operation is stopped. Do not write to this register while
operation is in progress.
■ Bit Configuration of Serial Mode Register (SMR)
Figure 13.2-3 shows the bit configuration of the serial mode register (SMR).
Figure 13.2-3 Bit Configuration of the Serial Mode Register (SMR)
Address: 000063
H
00006B
H
000073
H
■ Detailed Bit of Serial Mode Register (SMR)
The following describes each bit function of the serial mode register (SMR).
[bit7, bit6] MD1, MD0 (MoDe select): Setting of operating mode
These bits select a UART operating mode.
Table 13.2-1 shows the settings for the operating modes.
Table 13.2-1 Settings for Operating Modes
Mode
0
1
2
−
Note:
In Mode 1, which is CLK asynchronous mode (multiprocessor), more than one slave CPV can be
connected to one host CPU. Since this resource cannot identify the data format of received data,
however, only the master in multiprocessor mode is supported. Because the parity check function
cannot be used, set PEN of the SCR register to "0".
[bit5, bit4] (Reserved)
These bits are unused. Always write "1" to these bits.
bit 7 6
(ch.0)
MD1 MD0
(ch.1)
R/W R/W
(ch.2)
MD1 MD0
0 0
0 1
1 0
1 1
5 4 3 2
- - CS0 -
W
Operating mode
Asynchronous (start-stop synchronization) normal mode
[initial value]
Asynchronous (start-stop synchronization)
multiprocessor mode
CLK synchronous mode
Setting disabled
CHAPTER 13 UART
1 0 Initial value
00--0-0-
SCKE -
B
R/W
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