Overview Of Ppg Timer - Fujitsu FR60 Hardware Manual

CHAPTER 7 PPG TIMER
7.1

Overview of PPG Timer

The PPG timer can generate PWM wave forms with great precision and efficiency.
The MB91301 series has four built-in channels for the PPG timers.
■ Features of PPG Timer
• Each channel consists of the following elements:
• 16-bit down counter
• 16-bit data register with cycle setting buffer
• 16-bit compare register with duty setting buffer
• Pin controller
• One of the following can be selected for the 16-bit down counter clock:
Internal clock: φ
•
Internal clock: φ/4
•
Internal clock: φ/16
•
Internal clock: φ/64
•
• The counter value can be initialized to FFFF
• Each channel has a PPG output.
• Register
• Cycle set register: reload data register with buffer
• Duty set register: compare register with buffer
• Transfer from buffers is performed by using counter borrows.
• Pin control overview
• When a duty ratio match occurs, the counter value is set to "1". (Preferred)
• When a counter borrow occurs, the counter value is reset to "0".
• By using output value fix mode, all-low (or all-high) can be output easily.
• In addition, the polarity can be specified.
• An interrupt request can be generated by the following sources. Interrupt requests can be
used to start DMA transfer.
• Start of PPG timer
• Counter borrow (cycle match)
• Duty cycle match
• Counter borrow (cycle match) or duty ratio match
• Software or other interval timers can be used to specify that multiple channels are activated
at the same time. In addition, restart during operation can be specified.
• Detected request level can be selected from "rising edge", "falling edge" and "both edges".
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by using reset and counter borrows.
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