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User's Manual
A2 Processor
7.6.26 User Decrementer Interrupt
A user decrementer interrupt occurs when no higher priority exception exists, a user decrementer exception
exists (TSR[UDIS] = 1), and the interrupt is enabled (TCR[UDIE] = 1 and (MSR[EE] = 1 or MSR[GS] = 1)).
See Timer Facilities on page 387 for more information about User Decrementer exceptions.
Note: MSR[EE] also enables other interrupts. See Table 7-3 Interrupt and Exception Types on page 323.
When a user decrementer interrupt occurs, the interrupt processing registers are updated as indicated in the
following list (all registers not listed are unchanged) and instruction execution resumes at address IVPR[IVP]
|| 0x800.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Machine State Register (MSR)
Programming Note: Software is responsible for clearing the decrementer exception status by writing to
TSR[UDIS] before re-enabling MSR[EE] to avoid another, redundant user decrementer interrupt.
7.6.27 Performance Monitor Interrupt
A performance monitor interrupt occurs when no higher priority exception exists, a performance monitor
exception exists, and the interrupt is enabled (MSR[EE] = 1 or MSR[GS] = 1).
Note: MSR[EE] also enables other interrupts. See Table 7-3 Interrupt and Exception Types on page 323.
When a performance monitor interrupt occurs, the interrupt processing registers are updated as indicated in
the following list (all registers not listed are unchanged) and instruction execution resumes at address
IVPR[IVP] || 0x820.
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
CPU Interrupts and Exceptions
Page 356 of 864
SPV Set to 1 if the instruction causing the interrupt is an SPE
operation or a vector operation; otherwise, set to 0.
PT
Set to 1 if the cause of the interrupt is an LRAT miss excep-
tion on a page table translation. Set to 0 if the cause of the
interrupt is an LRAT miss exception on a tlbwe.
DATA Set to 1 if the interrupt is due to is an LRAT miss resulting
from a page table translation of a load, store or cache
management operand address; otherwise, set to 0.
EPID Set to 1 if the instruction causing the interrupt is an external
process ID instruction; otherwise, set to 0.
All other defined ESR bits are set to 0.
Set to the effective address of the next instruction to be executed.
Set to the contents of the MSR at the time of the interrupt.
CM set to EPCR[ICM].
CE, ME, DE Unchanged.
All other MSR bits set to 0.
Set to the effective address of the next instruction to be executed.
Set to the contents of the MSR at the time of the interrupt.
Version 1.3
October 23, 2012
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