Mel State Transactions - Motorola MPC750 User Manual

3.8 MEl State Transactions
Table 3-7 shows MEl state transitions for various operations. Bus operations are described
in Table 3-5.
Table 3-7. MEl State Transitions
Cache Bus
Current Next
Bus
Operation
WIM Cache Cache Cache Actions
Operation sync
State
State
Operation
Load Read No xOx I Same
1 Cast out of modified
Write-with-kill
(T= 0) block (as required)
2 Pass four-beat read Read
to memory queue
Load Read No xOx E,M Same Read data from cache
-
(T=O)
Load (T = 0) Read No x1x I Same Pass single-beat read to Read
memory queue
Load (T = 0) Read No x1x E I CRTRY read
-
Load (T = 0) Read No x1x M I CRTRY read (push Write-with-kill
sector to write queue)
Iwarx
Read Acts like other reads but bus operation uses special encoding
Store Write No OOx I Same Cast out of modified Write-with-kill
(T=O)
block (if necessary)
Pass RWITM to RWITM
memory queue
Store
Write
No
OOx E,M M Write data to cache
-
(T=O)
Store
~
stwcx.
Write No 10x I Same Pass single-beat write Write-with-flus
(T=O) to memory queue h
Store
~ stwcx.
Write No 10x
E
Same
Write data to cache
-
(T= 0)
Pass single-beat write Write-with-flus
to memory queue h
Store ~ stwcx.
Write No 10x M Same CRTRYwrite
-
(T = 0)
Push block to write Write-with-kill
queue
Store (T = 0) Write No x1x I Same Pass single-beat write Write-with-flus
or
stwcx.
to memory queue h
(WIM = 10x)
Store (T = 0) Write No x1x E I CRTRYwrite
-
or
stwcx.
(WIM = 10x)
3-32 MPC750 RISC Microprocessor User's Manual