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Timing Comments AssertionlNegation-Refer to the MPC750 hardware specifications
for timing comments. The L2SYNC_OUT signal is driven low
during assertion of HRESET.
7.2.9.16 L2 Sync In (L2SYNC_IN)-lnput
Following are the state meaning and timing comments for the L2SYNC_IN signal.
State Meaning
AssertedlNegated-Clock input for L2 clock synchronization. The
L2SYNC_IN signal is driven by the L2SYNC_OUT signal output.
Timing Comments AssertionlNegation-Refer to the MPC750 hardware specifications
for timing comments. The routing of this signal on the printed circuit
board should ensure that the rising edge at L2SYNC_IN is
coincident with the rising edge of the clock at the clock input of the
L2 cache memory devices.
7.2.9.17 L2 Low-Power Mode Enable (L2ZZ)-Output
Following are the state meaning and timing comments for the L2ZZ signal.
State Meaning
AssertedlNegated-Enables low-power mode for certain L2 cache
memory devices. Operation of the signal is enabled through the
L2CR.
Timing Comments AssertionlNegation-Occurs synchronously with the L2 clock when
the MPC750 enters and exits the nap or sleep power modes; after
negation of this signal, at least two L2 clock cycles will elapse before
L2 cache operations resume. The L2ZZ signal is driven low during
assertion of HRESET.
7.2.10 IEEE 1149.1a-1993 Interface Description
The MPC750 has five dedicated JTAG signals which are described in Table 7-6. The test
data input (TDI) and test data output (TDO) scan ports are used to scan instructions as well
as data into the various scan registers for JTAG operations. The scan operation is controlled
by the test access port (TAP) controller which in tum is controlled by the test mode select
(TMS) input sequence. The scan data is latched in at the rising edge of test clock (TCK).
Table 7-6. IEEE Interface Pin Descriptions
Signal Name
Input/Output
WeakPullup
IEEE 1149.1a Function
Provided
TOI
Input
Yes
Serial scan input signal
TOO
Output
No
Serial scan output signal
TMS
Input
Yes
TAP controller mode signal
TCK
Input
Yes
Scan clock
TRSi
Input
Yes
TAP controller reset
7-28
MPC750 RISC Microprocessor User's Manual
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