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For more information, see "Page History Recording" in Chapter 7, "Memory
Management," of The Programming Environments Manual.
5.4.2 Page Memory Protection
The MPC750 implements page memory protection as it is defined in Chapter 7, "Memory
Management," in The Programming Environments Manual.
5.4.3 TLB Description
The MPC750 implements separate 128-entry data and instruction TLBs to maximize
performance. This section describes the hardware resources provided in the MPC750 to
facilitate page address translation. Note that the hardware implementation of the MMU is
not specified by the architecture, and while this description applies to the MPC750, it does
not necessarily apply to other PowerPC processors.
5.4.3.1 TLB Organization
Because the MPC750 has two MMUs (IMMU and DMMU) that operate in parallel, some
of the MMU resources are shared, and some are actually duplicated (shadowed) in each
MMU to maximize performance. For example, although the architecture defines a single
set of segment registers for the MMU, the MPC750 maintains two identical sets of segment
registers, one for the IMMU and one for the DMMU; when an instruction that updates the
segment register executes, the MPC750 automatically updates both sets.
Each TLB contains 128 entries organized as a two-way set-associative array with 64 sets as
shown in Figure 5-7 for the DTLB (the ITLB organization is the same). When an address
is being translated, a set of two TLB entries is indexed in parallel with the access to a
segment register. If the address in one of the two TLB entries is valid and matches the 40-bit
virtual page number, that TLB entry contains the translation. If no match is found, a TLB
miss occurs.
Chapter 5. Memory Management
5-25
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