Motorola MPC750 User Manual page 360

Figure 9-8 shows a burst read-write-read memory access sequence when the L2 cache
interface is configured with late-write SRAM.
SRAMClk
L2CE
I I
~~~I--~--~~--~--~~--_I~/
L2WE
SRAMAddress
I I I I I I \
SRAMMemory
RO R1 R2 R8 R9 R10 R11
I I I
I I I I
SRAMData
I RO R1
\,,:,!,,",~~'\'!'!'::A.~
hiZ R8 R9 R10 R11
Note:
WQ is the last previous write that was queued in the late·write RAM.
Figure 9-8. Burst Read-Write-Read L2 Cache Access (Late-Write SRAM)
Figure 9-9 shows a burst read-modify-write memory access sequence when the L2 cache
interface is configured with late-write SRAM.
SRAMClk
L2CE
L2WE
SRAMAddress
I
I I I I
SRAMMemory
RO R1 R2 R3
I I I I
SRAMData
I
RO R1 R2
Note:
WQ is the last previous write that was queued in the late·write RAM.
Figure 9-9. Burst Read-Modify-Write L2 Cache Access (Late-Write SRAM)
Chapter 9. L2 Cache Interface Operation 9-13