Integer Store Gathering - Motorola MPC750 User Manual

The PowerPC architecture defines store with update instructions with r A = 0 as an invalid
form. In addition, it defines integer store instructions with the CR update option enabled
(Rc field, bit 31, in the instruction encoding
=
1)
to be an invalid form. Table 2-34
summarizes the integer store instructions.
Table 2-34. Integer Store Instructions
Name Mnemonic
Syntax
Store Byte stb rS,d(rA)
Store Byte Indexed stbx rS,rA,rB
Store Byte with Update stbu
rS,d(rA)
Store Byte with Update Indexed stbux rS,rA,rB
Store Half Word sth
rS,d(rA)
Store Half Word Indexed sthx
rS,rA,rB
Store Half Word with Update sthu rS,d(rA)
Store Half Word with Update Indexed sthux rS,rA,rB
Store Word stw
rS,d(rA)
Store Word Indexed stwx rS,rA,rB
Store Word with Update stwu rS,d(rA)
Store Word with Update Indexed stwux rS,rA,rB
2.3.4.3.5 Integer Store Gathering
The MPC750 performs store gathering for write-through accesses to nonguarded space or
to cache-inhibited stores to nonguarded space if the stores are 4 bytes and they are
word-aligned. These stores are combined in the load/store unit (LSU) to form a double
word and are sent out on the 60x bus as a single-beat operation. However, stores can be
gathered only if the successive stores that meet the criteria are queued and pending. Store
gathering takes place regardless of the address order of the stores. The store gathering
feature is enabled by setting HIDO[SGE]. Store gathering is done for both big- and
little-endian modes.
Store gathering is not done for the following:
• Cacheable stores
• Stores to guarded cache-inhibited or write-through space
• Byte-reverse store
• stwcx. and ecowx accesses
• Floating-point stores
• Store operations attempted during a hardware table search
If
store gathering is enabled and the stores do not fall under the above categories, an eieio
or sync instruction must be used to prevent two stores from being gathered.
2-48 MPC750 RISC Microprocessor User's Manual