Write-Through (Wt) Signal; Cache Inhibit (Ci) Signal - Motorola MPC750 User Manual

indicated by the assertion of TBST), TSIZ[0-2] are always set to ObOlO. Therefore, if the
TBST signal is asserted, the memory system should transfer a total of eight words (32
bytes), regardless of the TSIZ[0-2] encodings.
Table 8-1. Transfer Size Signal Encodings
TBST TSIZO TSIZ1 TSIZ2 Transfer Size
Asserted
a
1
a
Eight-word burst
Negated
a a a
Eight bytes
Negated
a a
1
One byte
Negated 0 1
a
Two bytes
Negated
a
1 1 Three bytes
Negated 1
a a
Four bytes
Negated 1
a
1 Five bytes (N/A)
Negated 1 1
a
Six bytes (N/A)
Negated 1
1
1 Seven bytes (N/A)
The basic coherency size of the bus is defined to be 32 bytes (corresponding to one cache
line). Data transfers that cross an aligned, 32-byte boundary either must present a new
address onto the bus at that boundary (for coherency consideration) or must operate as
noncoherent data with respect to the MPC750. The MPC750 never generates a bus
transaction with a transfer size of 5 bytes, 6 bytes, or 7 bytes.
8.3.2.2.3 Write-Through (WT) Signal
The MPC750 provides the WT signal to indicate a write-through operation as determined
by the WIM bit settings during address translation by the MMU. The WT signal is also
asserted for burst writes due to the execution of the debf and debst instructions, and snoop
push operations. The WT signal is deasserted for accesses caused by the execution of the
eeowx instruction. During read operations the MPC750 uses the WT signal to indicate
whether the transaction is an instruction fetch (WT set to 1), or a data read operation (WT
cleared to 0).
8.3.2.2.4 Cache Inhibit (CI) Signal
The MPC750 indicates the caching-inhibited status of a transaction (determined by the
setting of the WIM bits by the MMU) through the use of theCI signal. The CI signal is
asserted even if the Ll caches are disabled or locked. This signal is also asserted for bus
transactions caused by the execution of eciwx and eeowx instructions independent of the
address translation.
8-14
MPC750 RISC Microprocessor User's Manual