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the accesses are penormed as if MSR[DR] = 0 and G = 0 (that is, as nonguarded cacheable
operations in which coherency is required).
Table 5-8 defines a prioritized list of the R and C bit settings for all scenarios. The entries
in the table are prioritized from top to bottom, such that a matching scenario occurring
closer to the top of the table takes precedence over a matching scenario closer to the bottom
of the table. For example, if an stwcx. instruction causes a protection violation and there is
no reservation, the C bit is not altered, as shown for the protection violation case. Note that
in the table, load operations include those generated by load instructions, by the eciwx
instruction, and by the cache management instructions that are treated as a load with respect
to address translation. Similarly, store operations include those operations generated by
store instructions, by the ecowx instruction, and by the cache management instructions that
are treated as a store with respect to address translation.
Table 5-8. Model for Guaranteed Rand C Bit Settings
Causes Setting
of
R BH
Causes Setting ot C Bit
Priority
Scenario
OEA
MPC750
OEA
MPC750
1
No-execute protection violation
No
No
No
No
2
Page protection violation
Maybe
Yes
No
No
3
Out-ol-order instruction fetch or load operation
Maybe
No
No
No
4
Out-ol-order store operation. Would be required
Maybe
1
No
No
No
by the sequential execution model in the absence
of system-caused or imprecise exceptions, or of
floating-point assist exception for instructions that
would cause no other kind of precise exception.
5
All other out-of-order store operations
Maybe
1
No
Maybe
1
No
6
Zero-length load (Iswx)
Maybe
No
No
No
7
Zero-length store (stswx)
Maybe
1
No
Maybe
1
No
8
Store conditional (stwex.) that does not store
Maybe
1
Yes
Maybe
1
Yes
9
In-order instruction fetch
Yes
2
Yes
No
No
10
Load instruction or eeiwx
Yes
Yes
No
No
11
Store instruction, eeowx or debz instruction
Yes
Yes
Yes
Yes
12
iebi, debt, or debtst instruction
Maybe
No
No
No
13
debst or debt instruction
Maybe
Yes
No
No
14
debi instruction
Maybe
1
Yes
Maybe
1
Yes
Notes:
1
If C is set, R is guaranteed to be set also.
2
Includes the case in which the instruction is fetched out of order and R is not set (does not apply for MPC750).
5-24
MPC750 RISC Microprocessor User's Manual
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