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1.2.9 Clocking
The MPC750 requires a single system clock input, SYSCLK, that represents the bus
interface frequency. Internally, the processor uses a phase-locked loop (PLL) circuit to
generate a master core clock that is frequency-multiplied and phase-locked to the SYSCLK
input. This core frequency is used to operate the internal circuitry.
The PLL is configured by the PLL_CFG[0-3] signals, which select the multiplier that the
PLL uses to multiply the SYSCLK frequency up to the internal core frequency. The
feedback in the PLL guarantees that the processor clock is phase locked to the bus clock,
regardless of process variations, temperature changes, or parasitic capacitances. The PLL
also ensures a 50% duty cycle for the processor clock.
The MPC750 supports various processor-to-bus clock frequency ratios, although not all
ratios are available for all frequencies. Configuration of the processor/bus clock ratios is
displayed through a MPC750-specific register, HID1. For information about supported
clock frequencies, see the MPC750 hardware specifications.
1.3 MPC750 Microprocessor: Implementation
The PowerPC architecture is derived from the POWER architecture (Performance
Optimized with Enhanced RISC architecture). The PowerPC architecture shares the
benefits of the POWER architecture optimized for single-chip implementations. The
PowerPC architecture design facilitates parallel instruction execution and is scalable to take
advantage of future technological gains.
This section describes the PowerPC architecture in general, and specific details about the
implementation of the MPC750 as a low-power, 32-bit member of the PowerPC processor
family. The structure of this section follows the organization of the user's manual; each
subsection provides an overview of each chapter.
•
Registers and programming model-Section lA, "PowerPC Registers and
Programming Model," describes the registers for the operating environment
architecture common among PowerPC processors and describes the programming
model. It also describes the registers that are unique to the MPC750. The
information in this section is described more fully in Chapter 2, "MPC750 Processor
Programming Model."
• Instruction set and addressing modes-Section 1.5, "Instruction Set," describes the
PowerPC instruction set and addressing modes for the PowerPC operating
environment architecture, and defines and describes the PowerPC instructions
implemented in the MPC750. The information in this section is described more fully
in Chapter 2, "MPC750 Processor Programming Model."
Chapter 1. Overview
1-19
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