Table of Contents
Advertisement
6.6.1.1 Branch Resolution Resource Requirements
The following is a list of branch instructions and the resources required to avoid stalling the
fetch unit in the course of branch resolution:
•
The beIr instruction requires LR availability.
• The bcctr instruction requires CTR availability.
• Branch and link instructions require shadow LR availability.
The "branch conditional on counter decrement and the CR" condition requires CTR
availability or the CR condition must be false, and the MPC750 cannot execute
instructions after an unresolved predicted branch when the BPU encounters a
branch.
• A branch conditional on CR condition cannot be executed following an unresolved
predicted branch instruction.
6.6.1.2 Dispatch Unit Resource Requirements
The following is a list of resources required to avoid stalls in the dispatch unit. IQ[O] and
IQ[1] are the two dispatch entries in the instruction queue:
•
Requirements for dispatching from IQ[O] are as follows:
-
Needed execution unit available
-
Needed GPR rename registers available
-
Needed FPR rename registers available
-
Completion queue is not full.
-
A completion-serialized instruction is not being executed.
•
Requirements for dispatching from IQ[l] are as follows:
-
Instruction in IQ[O] must dispatch.
-
Instruction dispatched by IQ[O] is not completion- or refetch-serialized.
-
Needed execution unit is available (after dispatch from IQ[O]).
-
Needed GPR rename registers are available (after dispatch from IQ[O]).
-
Needed FPR rename register is available (after dispatch from IQ[O]).
-
Completion queue is not full (after dispatch from IQ[O]).
6.6.1.3 Completion Unit Resource Requirements
The following is a list of resources required to avoid stalls in the completion unit; note that
the two completion entries are described as CQ[O] and CQ[l], where CQ[O] is the
completion queue located at the end of the completion queue (see Figure 6-4).
•
Requirements for completing an instruction from CQ[O] are as follows:
-
Instruction in CQ[O] must be finished.
-
Instruction in CQ[O] must not follow an unresolved predicted branch.
-
Instruction in CQ[O] must not cause an exception.
6-30
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
