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Cache lines are selected for replacement based on a pseudo least-recently-used (PLRU)
algorithm. Each time a cache line is accessed, it is tagged as the most-recently-used line of
the set. When a miss occurs, and all eight lines in the set are marked as valid, the least
recently used line is replaced with the new data. When data to be replaced is in the modified
state, the modified data is written into a write-back buffer while the missed data is being
read from memory. When the load completes, the MPC750 then pushes the replaced line
from the write-back buffer to the L2 cache (if enabled), or to main memory in a burst write
operation.
8.1.2 Operation of the L2 Cache
The MPC750 provides an on-chip, two-way set associative tag memory, and a dedicated L2
cache port with support for up to 1 Mbyte of external synchronous SRAMs for data storage.
The L2 cache normally operates in copy-back mode and supports system cache coherency
through snooping. Designers should note that the MPC740 does not implement the on-chip
L2 tag memory, or the signals required for the support of the external SRAMs, and memory
accesses go directly to the bus interface unit.
The L2 cache receives independent memory access requests from both the Ll instruction
and data caches. The LI accesses are compared to the L2 cache tags and the data or
instructions are forwarded from the L2 to the Ll cache if there is a cache hit, or are
forwarded on to the bus interface unit if there is an L2 cache miss, or if the address being
accessed is from a page marked as caching-inhibited. Burst read accesses that miss in the
L2 cache initiate a load operation from the bus interface. As the load operation transfers
data to the L 1 cache, the data is also loaded into the L2 cache, and marked as valid
unmodified in the L2 cache tags. An Ll load, store, or castout operation can cause an L2
cache block allocation resulting in the castout of an L2 cache block marked modified to the
bus interface. For additional information about the operation of the L2 cache, refer to
Chapter 9, "L2 Cache Interface Operation."
8.1.3 Operation of the System Interface
Memory accesses can occur in single-beat (1,2,3,4, and 8 bytes) and four-beat (32 bytes)
burst data transfers. The address and data buses are independent for memory accesses to
support pipelining and split transactions. The MPC750 can pipeline as many as two
transactions and has limited support for out-of-order split-bus transactions.
Access to the system interface is granted through an external arbitration mechanism that
allows devices to compete for bus mastership. This arbitration mechanism is flexible,
allowing the MPC750 to be integrated into systems that implement various fairness ane!
bus-parking procedures to avoid arbitration overhead.
8-4
MPC750 RISC Microprocessor User's Manual
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