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Chapter 3
L 1 Instruction and Data Cache
Operation
The MPC750 microprocessor contains separate 32-Kbyte, eight-way set aSSOCiative
instruction and data caches to allow the execution units and registers rapid access to
instructions and data. This chapter describes the organization of the on-chip instruction and
data caches, the MEl cache coherency protocol, cache control instructions, various cache
operations, and the interaction between the caches, the load/store unit (LSU), the
instruction unit, and the bus interface unit (BIU).
Note that in this chapter, the term 'multiprocessor' is used in the context of maintaining
cache coherency. These multiprocessor devices could be actual processors or other devices
that can access system memory, maintain their own caches, and function as bus masters
requiring cache coherency.
The MPC750 cache implementation has the following characteristics:
•
There are two separate 32-Kbyte instruction and data caches (Harvard architecture).
Both instruction and data caches are eight-way set associative.
• The caches implement a pseudo least-recently-used (PLRU) replacement algorithm
within each set.
•
The cache directories are physically addressed. The physical (real) address tag is
stored in the cache directory.
•
Both the instruction and data caches have 32-byte cache blocks. A cache block is the
block of memory that a coherency state describes, also referred to as a cache line.
• Two coherency state bits for each data cache block allow encoding for three states:
-
Modified (Exclusive) (M)
-
Exclusive (Unmodified) (E)
-
Invalid (I)
• A single coherency state bit for each instruction cache block allows encoding for two
possible states:
-
Invalid (INV)
-
Valid (VAL)
Chapter
3. L 1 Instruction and Data Cache Operation
3-1
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