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7.2.9.12 L2 Write Enable (L2WE)-Output
Following are the state meaning and timing comments for the L2WE signal.
State Meaning
Asserted-Indicates that the MPC750 is performing a write
operation to the L2 cache memory.
Negated-Indicates that the MPC750 is not performing an L2 cache
memory write operation.
Timing Comments
AssertionlNegation-May occur on any cycle. L2WE is driven high
during HRESET assertion.
7.2.9.13 L2 Clock Out A (L2CLK_OUTA)-Output
Following are the state meaning and timing comments for the L2CLK_OUTA signal.
State Meaning
AssertedlNegated-Clock output for L2 cache memory devices. The
L2CLK_OUTA signal is identical and synchronous with the
L2CLK_OUTB signal, and provides the capability to drive up to four
L2 cache memory devices. If differential L2 clocking is configured
through the setting of the L2CR, the L2CLK_OUTB signal is driven
phase inverted with relation to the L2CLK_OUTA signal.
Timing Comments
AssertionlNegation-Refer to the MPC750 hardware specifications
for timing comments. The L2CLK_OUTA signal is driven low
during assertion of HRESET.
7.2.9.14 L2 Clock Out B (L2CLK_OUTB)-Output
Following are the state meaning and timing comments for the L2CLK_OUTB signal.
State Meaning
AssertedlNegated-Clock output for L2 cache memory devices. The
L2CLK_OUTB signal is identical and synchronous with the
L2CLK_OUTA signal, and provides the capability to drive up to four
L2 cache memory devices. If differential L2 clocking is configured
through the setting of the L2CR, the L2CLK_ OUTA signal is driven
phase inverted with relation to the L2CLK_OUTB signal.
Timing Comments
AssertionlNegation-Refer to the MPC750 hardware specifications
for timing comments. The L2CLK_OUTB signal is driven low
during assertion of HRESET.
7.2.9.15 L2 Sync Out (L2SYNC_OUT)-Output
Following are the state meaning and timing comments for the L2SYNC_OUT signal.
State Meaning
AssertedlNegated--Clock output for L2 clock synchronization. The
L2SYNC_ OUT signal should be routed half of the trace length to the
L2 cache memory devices and returned to the L2SYNC_IN signal
input.
Chapter 7. Signal Descriptions
7-27
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