Table of Contents
Advertisement
~
Reserved
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Figure 4-3. Machine State Register (MSR)
The MSR bits are defined in Table 4-4_
Table 4-4. MSR Bit Settings
Bit(s}
Name
Description
0
-
Reserved. Full function.
1
1-4
-
Reserved. Partial function.
1
5-9
-
Reserved. Full function.
1
10-12
-
Reserved. Partial function.
1
13
POW
Power management enable
0
Power management disabled (normal operation mode).
1
Power management enabled (reduced power mode).
Power management functions are implementation-dependent. See Chapter
10,
"Power and Thermal
Management."
14
-
Reserved. Implementation-specific
15
ILE
Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE) to select the
end ian mode for the context established by the exception.
16
EE
External interrupt enable
0
The proQessor delays recognition of external interrupts and decrementer exception conditions.
1
The processor is enabled to take an external interrupt or the decrementer exception.
17
PR
Privilege level
0
The processor can execute both user- and supervisor-level instructions.
1
The processor can only execute user-level instructions.
18
FP
Floating-point available
0
The processor prevents dispatch of floating-paint instructions, including floating-point loads,
stores, and moves.
1
The processor can execute floating-point instructions and can take floating-paint enabled
program exceptions.
19
ME
Machine check enable
0
Machine check exceptions are disabled.
1
Machine check exceptions are enabled.
20
FEO
IEEE floating-point exception mode
0
(see Table
4-5).
21
SE
Single-step trace enable
0
The processor executes instructions normally.
1
The processor generates a single-step trace exception upon the successful execution of every
instruction except rfi, isync, and sc. Successful execution means that the instruction caused
no other exception.
4-8
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
