Motorola MPC750 User Manual page 104

Table 2-18. L2CR Bit Settings
Bit Name Function
a
L2E L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2
cache unit receives. Before enabling the L2 cache, the L2 clock must be configured through
L2CR[2CLK], and the L2 DLL must stabilize (see the hardware specifications). All other L2CR bits
must be set appropriately. The L2 cache may need to be invalidated globally.
1 L2PE L2 data parity generation and checking enable. Enables parity generation and checking for the L2
data RAM interface. When disabled, generated parity is always zeros.
2-3 L2SIZ L2 size-Should be set according to the size of the L2 data RAMs used. A 256-Kbyte L2 cache
requires a data RAM configuration of 32 Kbytes x 64 bits; a 512-Kbyte L2 cache requires a
configuration of 64 Kbyte x 64 bits; a 1-Mbyte L2 cache requires a configuration of 128K x 64 bits.
00 Reserved
01 256 Kbyte
10 512 Kbyte
11
1 Mbyte
4-6 L2CLK L2 clock ratio (core-to-L2 frequency divider). Specifies the clock divider ratio based from the core
clock frequency that the L2 data RAM interface is to operate at. When these bits are cleared, the L2
clock is stopped and the on-chip DLL for the L2 interface is disabled. For nonzero values, the
processor generates the L2 clock and the on-chip DLL is enabled. After the L2 clock ratio is chosen,
the DLL must stabilize before the L2 interface can be enabled. (See the hardware specifications). The
resulting L2 clock frequency cannot be slower than the clock frequency of the 60x bus interface.
000 L2 clock and DLL disabled
001
~1
010 ~1.5
011 Reserved
100 ~2
101 ~2.5
110 ~3
111 Reserved
7-8 L2RAM L2 RAM type-Configures the L2 RAM interface for the type of synchronous SRAMs used:
Flow-through (register-buffer) synchronous burst SRAMs that clock addresses in and flow data out
Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out
.
Late-write synchronous SRAMs, for which the MPC750 requires a pipelined (register-register)
configuration. Late-write RAMs require write data to be valid on the cycle after WE is asserted,
rather than on the same cycle as the write enable as with traditional burst RAMs.
For burst RAM selections, the MPC750 does not burst data into the L2 cache, it generates an address
for each access. Pipelined SRAMs may be used for all L2 clock modes. Note that flow-through
SRAMs can be used only for L2 clock modes divide-by-2 or slower (divide-by-1 and divide-by-1.5 not
allowed).
00 Flow-through (register-buffer) synchronous burst SRAM
01 Reserved
10 Pipelined (register-register) synchronous burst SRAM
11 Pipelined (register-register) synchronous late-write SRAM
9
L2DO L2 data-only. Setting this bit enables data-only operation in the L2 cache. For this operation, only
transactions from the L 1 data cache can be cached in the L2 cache, which treats all transactions from
the L 1 instruction cache as cache-inhibited (bypass L2 cache, no L2 checking done). This bit is
provided for L2 testing only.
10 L21 L2 global invalidate. Setting L21 invalidates the L2 cache globally by clearing the L2 bits including
status bits. This bit must not be set while the L2 cache is enabled.
Chapter 2. MPC750 Processor Programming Model 2-25