Table of Contents
Advertisement
translation is enabled. Note that when address translation is disabled (real addressing
mode), the default WIMG bits cause the I bit to be cleared (accesses are assumed to be
cacheable), and thus the accesses are weakly ordered. Refer to Section 5.2, "Real
Addressing Mode," for a description of the WIMG bits when address translation is disabled.
The MPC750 does not provide support for direct-store segments. Operations attempting to
access a direct-store segment will invoke a OSI exception. For additional information about
OSI exceptions, refer to Section 4.5.3, "OSI Exception (Ox00300)."
3.3.5.1 Performed Loads and Stores
The PowerPC architecture defines a performed load operation as one that has the addressed
memory location bound to the target register of the load instruction. The architecture
defines a performed store operation as one where the stored value is the value that any other
processor will receive when executing a load operation (that is of course, until it is changed
again).
With respect to the MPC750, caching-allowed (WIMG
=
xOxx) loads and
caching-allowed, write-back (WIMG
=
OOxx) stores are performed when they have
arbitrated to address the cache block. Note that in the event of a cache miss, these storage
operations may place a memory request into the processor's memory queue, but such
operations are considered an extension to the state of the cache with respect to snooping
bus operations. Caching-inhibited (WIMG = xlxx) loads, caching-inhibited (WIMG =
xlxx) stores, and write-through (WIMG
=
lxxx) stores are performed when they have been
successfully presented to the external60x bus.
3.3.5.2 Sequential Consistency of Memory Accesses
The PowerPC architecture requires that all memory operations executed by a single
processor be sequentially consistent with respect to that processor. This means that all
memory accesses appear to be executed in program order with respect to exceptions and
data dependencies.
The MPC750 achieves sequential consistency by operating a single pipeline to the
cache/MMU. All memory accesses are presented to the MMU in exact program order and
therefore exceptions are determined in order. Loads are allowed to bypass stores once
exception checking has been performed for the store, but data dependency checking is
handled in the load/store unit so that a load will not bypass a store with an address match.
Note that although memory accesses that miss in the cache are forwarded to the memory
queue for future arbitration for the external bus, all potential synchronous exceptions have
been resolved before the cache. In addition, although subsequent memory accesses can
address the cache, full coherency checking between the cache and the memory queue is
provided to avoid dependency conflicts.
3.3.5.3 Atomic Memory References
The PowerPC architecture defines the Load Word and Reserve Indexed (lwarx) and the
Store Word Conditional Indexed (stwex.) instructions to provide an atomic update function
for a single, aligned word of memory. These instructions can be used to develop a rich set
of multiprocessor synchronization primitives. Note that atomic memory references
Chapter 3. L 1 Instruction and Data Cache Operation
3-11
Advertisement
Table of Contents
