Table of Contents
Advertisement
As shown in Figure 3-6, the first quad word contains the address of the load/store or
instruction fetch that missed the cache. This minimizes latency by allowing the critical code
or data to be forwarded to the processor before the rest of the block is filled. For all other
burst operations, however, the entire block is transferred in order (oct-word-aligned).
Critical-double-word-first fetching on a cache miss applies to both the data and instruction
cache.
MPC750 Cache Address
Bits (27,. 28)
00
A
01
B
10
11
C
D
If the address requested is in double-word A, the address placed on the bus is that of double-word A, and
the four data beats are ordered in the following manner:
Beat
o
2
A
B
C
D
If the address requested is in double-word C, the address placed on the bus will be that of double-word
C, and the four data beats are ordered in the following manner:
Beat
o
2
3
C
D
A
B
Figure 3-6. Double-Word Address Ordering-Critical Double Word First
3.6.1 Read Operations and the MEl Protocol
The MEl coherency protocol affects how the MPC750 data cache performs read operations
on the 60x bus. All reads (except for caching-inhibited reads) are encoded on the bus as
read-with-intent-to-modify (RWITM) to force flushing of the addressed cache block from
other caches in the system.
The MEl coherency protocol also affects how the MPC750 snoops read operations on the
60x bus. All reads snooped from the 60x bus (except for caching-inhibited reads) are
interpreted as RWITM to cause flushing from the MPC750's cache. Single-beat reads
(TBST negated) are interpreted by the MPC750 as caching inhibited.
These actions for read operations allow the MPC750 to operate successfully (coherently)
on the bus with other bus masters that implement either the three-state MEl or a four-state
MESI cache coherency protocol.
Chapter 3. L 1 Instruction and Data Cache Operation
3-23
Advertisement
Table of Contents
