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7. In cycle 7, instruction 7 is in the final FPU execute stage and instructions 8-10 wait
in the completion queue. Instructions 11 and 12 are dispatched to the IU2 and FPU,
respectively. Note that at this point the completion queue is full. Two more
instructions (15 and 16, which are shown only in the instruction queue) are fetched.
8.
In
cycle 8, instructions 7-11 are through executing. Instructions 7 and 8 complete,
write back, and vacate the completion queue. Because the completion queue is full,
instructions 13 and 14 cannot be dispatched and must remain in the instruction
queue. Only the FPU is executing during this cycle (instruction 12). Additional
instructions (instructions 16 and 17, shown only in the instruction queue) are
fetched, filling the instruction queue.
9.
In
cycle 9, two more instructions (instructions 7 and 8) are retired from the
completion queue allowing instructions 13 and 14 to be dispatched, again filling the
completion queue. No instructions are fetched on this cycle because the instruction
queue was full on the previous clock cycle.
6.3.2.3 Cache Miss
Figure 6-6 shows an instruction fetch that misses both the on-chip cache and L2 cache. A
processor/bus clock ratio is 1:2 is used. The same instruction sequence is used as in
Section 6.3.2.2, "Cache Hit," however in this example, the branch target instruction is not
in either the L1 or L2 cache. Because the target instruction is not in the L1 cache, it cannot
be in the BTIC.
A cache miss, extends the latency of the fetch stage, so in this example, the fetch stage
shown represents not only the time the instruction spends in the IQ, but the time required
for the instruction to be loaded from system memory, beginning in clock cycle 2.
During clock cycle 3, the target instruction for the b instruction is not in the BTIC, the
instruction cache or the L2 cache;
therefor~,
a memory access must occur. During clock
cycle 5, the address of the block of instructions is sent to the system bus. During clock cycle
7, two instructions (64 bits) are returned from memory on the first beat and are forwarded
both to the cache and the instruction fetcher.
6-14
MPC750 RISC Microprocessor User's Manual
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