Motorola MPC750 User Manual page 44

Risc
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128,Bit
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Fetcher
L
Branch Processing
(4 Instructions)
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Unit
Instruction MMU
Additional Features
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• Time Base Counter/Decrementer
Instruction Queue
64 Entry···
LR
SRs
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• Clock Multiplier
(6 Word)
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(Shadow)
IBAT
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• JTAG/COP Interface
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Array I
Tags
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II Reservation Station II Reservation Station II Reservation Station I
Reservation Station
I
Reservation Station
GPR File
(2 Entry)
FPR File
~
~
Rename Buffers
-'
Rename Buffers
(6)
(6)
I
System Register
~
1;2~~~
load/Store Unit
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Floating-Point
Integer Unitt
Integer Unit 2
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Store Queue
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32-Bit
32-Bit
1
1
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Completion Unit
SOx Bus Interface Unit
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Data MMU
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,-----
64-Bit
Instruction Fetch Queue
I
l2 Bus Interface
Reorder Buffer
SRs
1
I
I
Unit
(6 Entry)
(Original)
L 1 Castout Queue
~
~
DBAT
H
Tags
I
I
L2 Castout Queue
Array
32-Kbyte
I
I
~
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Cache
Data Load Queue
I
L2 Controller
I
I
I
~
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I
32-Bit Address Bus
I
L2 Tags
64-Bit Data Bus
I
I
Not in the MPC740
~
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 17=-BitU Address-Bus-
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64-Bit L2 Data Bus

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