Page Address Translation Selection - Motorola MPC750 User Manual

5.1.6.2 Page Address Translation Selection
If address translation is enabled and the effective address information does not match a BAT
array entry, the segment descriptor must be located. When the segment descriptor is located,
the T bit in the segment descriptor selects whether the translation is to a page or to a
direct-store segment as shown in Figure 5-6. For 32-bit implementations, the segment
descriptor for an access is contained in one of 16 on-chip segment registers; effective
address bits EA[O-3] select one of the 16 segment registers.
Note that the MPC750 does not implement the direct-store interface, and accesses to these
segments cause a DSI or lSI exception. In addition, Figure 5-6 also shows the way in which
the no-execute protection is enforced; if the N bit in the segment descriptor is set and the
access is an instruction fetch, the access is faulted as described in Chapter 7, "Memory
Management," in The Programming Environments Manual. Note that the figure shows the
flow for these cases as described by the PowerPC OEA, and so the TLB references are
shown as optional. Because the MPC750 implements TLBs, these branches are valid and
are described in more detail throughout this chapter.
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MPC750 RISC Microprocessor User's Manual