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7.2.9.7.5 TLBI Sync (TLBISYNC)-Input
The TLBI Sync (TLBISYNC) signal is an input-only signal on the MPC750. Following are
the state meaning and timing comments for the TLBISYNC signal.
State Meaning
Asserted-Indicates that instruction execution should stop after
execution of a tlbsync instruction.
Negated-Indicates that the instruction execution may continue or
resume after the completion of a tlbsync instruction.
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Timing Comments AssertionlNegation-May occur on any cycle. The TLBISYNC
signal must be held negated during HRESET.
7.2.9.7.6 L2 Cache Interface
The MPC750's dedicated L2 cache interface provides all the signals required for the
support of up to 1 Mbyte of synchronous SRAM for data storage. The use of the L2 data
parity (L2DP[0-7]) and L2 low-power mode enable (L2ZZ) signals is optional, and
depends on the SRAMs selected for use with the MPC750. Note that the least-significant
bit of L2 address (L2ADDR[16-0]) signals is identified as bit 0, and the most-significant
bit is identified as bit 16.
Note that the L2 cache interface is not implemented in the MPC740.
7.2.9.8 L2 Address (L2ADDR[16-0])-Output
Following are the state meaning and timing comments for the L2 address output signals.
State Meaning
AssertedlNegated-Represents the address of the data to be
transferred to the L2 cache. The L2 address bus is configured with
bit 0 as the least-significant bit. Address bit 14 determines which
cache tag set is selected.
Timing Comments AssertionlNegation-Driven valid by the MPC750 during read and
write operations; driven with static data when the L2 cache memory
is not being accessed.
7.2.9.9 L2 Data (L2DATA[O-63])
The data bus (L2DATA[0-63]) consists of 64 signals that are both input and output on the
MPC750.
7.2.9.9.1 L2 Data (L2DATA[O-63])-Output
Following are the state meaning and timing comments for the L2 data output signals.
State Meaning
AssertedlNegated-Represents the state of data during a data write
transaction; data is always transferred as double words.
Timing Comments AssertionlNegation-Driven valid by MPC750 during write
operations; driven with static data when the L2 cache memory is not
being accessed by a read operation.
Chapter 7. Signal Descriptions
7-25
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