Appendix B Instructions Not Implemented - Motorola MPC750 User Manual

Appendix B
Instructions Not Implemented
This appendix provides a list of the 32-bit and 64-bit PowerPC instructions that are not
implemented in the MPC750 microprocessor. Note that any attempt to execute instructions
that are not implemented on the MPC750 will generate an illegal instruction exception.
Note that exceptions are referred to as interrupts in the architecture specification.
Table B-1 provides the 32-bit PowerPC instructions that are optional to the PowerPC
architecture but not implemented by the MPC750.
Table B-1. 32-Bit Instructions Not Implemented by the MPC750 Processor
Mnemonic Instruction
dcba Data Cache Block Allocate
fsqrt Floating Square Root (Double-Precision)
fsqrts Floating Square Root Single
tibia TLB Invalidate All
Table B-2 provides a list of 64-bit instructions that are not implemented by the MPC750.
Table B-2. 64-Bit Instructions Not Implemented by the MPC750 Processor
Mnemonic
Instruction
cntlzd Count Leading Zeros Double Word
divd Divide Double Word
divdu Divide Double Word Unsigned
extsw Extend Sign Word
fcfid Floating Convert From Integer Double Word
fctid Floating Convert to Integer Double Word
fctidz Floating Convert to Integer Double Word with Round toward Zero
Id Load Double Word
Idarx Load Double Word and Reserve Indexed
Idu Load Double Word with Update
Appendix B. Instructions Not Implemented 8-1