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Any number of bus transactions by other bus masters can be attempted between any of these
steps.
Note the following regarding DBWO:
•
DBWO can be asserted if no data bus read is pending, but it has no effect on write
ordering.
•
The ordering and presence of data bus writes is determined by the writes in the write
queues at the time BG is asserted for the write address (not DBG). If a particular
write is desired (for example, a cache-line-snoop-push-out operation), then BG must
be asserted after that particular write is in the queue and it must be the highest
priority write in the queue at that time. A cache-line-snoop-push-out operation may
be the highest priority write, but more than one may be queued.
•
Because more than one write may be in the write queue when DBG is asserted for
the write address, more than one data bus write may be enveloped by a pending data
bus read.
The arbiter must monitor bus operations and coordinate the various masters and slaves with
respect to the use of the data bus when DBWO is used. Individual DBG signals associated
with each bus device should allow the arbiter to synchronize both pipelined and
split-transaction bus organizations. Individual DBG and DBWO signals provide a primitive
form of source-level tagging for the granting of the data bus.
Note that use of the DBWO signal allows some operation-level tagging with respect to the
MPC750 and the use of the data bus.
Chapter 8. System Interface Operation
8-39
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