Figure 3-17. Bus Arbitration Unit State Diagrams - Motorola MC68306 User Manual

When a bus request is made after the MPU has begun a bus cycle and before AS has
been asserted (S0), the special sequence shown in Figure 3-20 applies. Instead of being
asserted on the next rising edge of clock, BG is delayed until the second rising edge
following its internal assertion.
RA
R = Bus Request Internal
A = Bus Grant Acknowledge Internal
G = Bus Grant
T = Three-state Control to Bus Control Logic
X = Don't Care

Figure 3-17. Bus Arbitration Unit State Diagrams

3-18
1
RA
GT
RA
XX
XA
GT
RA
RA
(a) 3-Wire Bus Arbitration
R
GT
STATE 1
X
GT
STATE 2
R
(b) 2-Wire Bus Arbitration
R
MC68306 USER'S MANUAL
RA
1
GT
XA
RA
GT
RA
R+A
GT
RA
GT
XX
GT
RA
R
GT
R
STATE 0
GT
R
STATE 4
GT
X
STATE 3
RA
RX
Notes:
1. State machine will not change if
the bus is S0 or S1. Refer to
BUS ARBITRATION CONTROL.
2. The address bus will be placed in
the high-impedance state if T is
asserted and AS is negated.
MOTOROLA
5.2.3.