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8.4.2 Data Bus Write Only
As a result of address pipe lining, the MPC750 may have up to two data tenures queued to
perform when it receives a qualified DBG. Generally, the data tenures should be performed
in strict order (the same order) as their address tenures were performed. The MPC750,
however, also supports a limited out-of-order capability with the data bus write only
(DBWO) input. When recognized on the clock of a qualified DBG, DBWO may direct the
MPC750 to perform the next pending data write tenure even if a pending read tenure would
have normally been performed first. For more information on the operation ofDBWO, refer
to Section 8.10, "Using Data Bus Write Only."
If the MPC750 has any data tenures to perform, it always accepts data bus mastership to
perform a data tenure when it recognizes a qualified DBG. If DBWO is asserted with a
qualified DBG and no write tenure is queued to run, the MPC750 still takes mastership of
the data bus to perform the next pending read data tenure.
Generally, DBWO should only be used to allow a copy-back operation (burst write) to
occur before a pending read operation.
If
DBWO is used for single-beat write operations,
it may negate the effect of the eieio instruction by allowing a write operation to precede a
program-scheduled read operation.
8.4.3 Data Transfer
The data transfer signals include DR[O-31], DL[0-31], and DP[0-7]. For memory
accesses, the DR and DL signals form a 64-bit data path for read and write operations.
The MPC750 transfers data in either single- or four-beat burst transfers. Single-beat
operations can transfer from 1 to 8 bytes at a time and can be misaligned; see
Section 8.3.2.4, "Effect of Alignment in Data Transfers." Burst operations always transfer
eight words and are aligned on eight-word address boundaries. Burst transfers can achieve
significantly higher bus throughput than single-beat operations.
The type of transaction initiated by the MPC750 depends on whether the code or data is
cacheable and, for store operations whether the cache is in write-back or write-through
mode, which software controls on either a page or block basis. Burst transfers support
cacheable operations only; that is, memory structures must be marked as cacheable (and
write-back for data store operations) in the respective page or block descriptor to take
advantage of burst transfers.
The MPC750 output TBST indicates to the system whether the current transaction is a
single- or four-beat transfer (except during eciwx/ecowx transactions, when it signals the
state of EAR[28]). A burst transfer has an assumed address order. For load or store
operations that miss in the cache (and are marked as cacheable and, for stores, write-back
in the MMU), the MPC750 uses the double-word-aligned address associated with the
critical code or data that initiated the transaction. This minimizes latency by allowing the
critical code or data to be forwarded to the processor before the rest of the cache line is
Chapter 8. System Interface Operation
8-21
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