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An external interrupt may be delayed by other higher priority exceptions or if MSR[EE] is
cleared when the exception occurs. Register settings for this exception are described in
Chapter 6, "Exceptions," in The Programming Environments Manual.
When an external interrupt exception is taken, instruction fetching resumes at offset
Ox00500 from the physical base address indicated by MSR[IP].
4.5.6 Alignment Exception (Ox00600)
The MPC750 implements the alignment exception as defined by the PowerPC architecture
(OEA). An alignment exception is initiated when any of the following occurs:
•
The operand of a floating-point load or store is not word-aligned.
• The operand of Imw, stmw, Iwarx, or stwcx. is not word-aligned.
• The operand of dcbz is in a page that is write-through or cache-inhibited.
•
An attempt is made to execute dcbz when the data cache is disabled.
•
An eciwx or ecowx is not word-aligned
• A multiple or string access is attempted with MSR[LE] set
Note that in the MPC750, a floating-point load or store to a direct-store segment causes a
DSI exception rather than an alignment exception, as specified by the PowerPC
architecture. For more information, see 4.5.3, "DSI Exception (Ox00300)."
4.5.7 Program Exception (Ox00700)
The MPC750 implements the program exception as it is defined by the PowerPC
architecture (OEA). A program exception occurs when no higher priority exception exists
and one or more of the exception conditions defined in the OEA occur.
The MPC750 invokes the system illegal instruction program exception when it detects any
instruction from the illegal instruction class. The MPC750 fully decodes the SPR field of
the instruction. If an undefined SPR is specified, a program exception is taken.
The UISA defines mtspr and mfspr with the record bit (Rc) set as causing a program
exception or giving a boundedly-undefined result. In the MPC750, the appropriate
condition register (CR) should be treated as undefined. Likewise, the PowerPC architecture
states that the Floating Compared Unordered (fcmpu) or Floating Compared Ordered
(fcmpo) instruction with the record bit set can either cause a program exception or provide
a boundedly-undefined result. In the MPC750, an the BF field in an instruction encoding
for these cases is considered undefined.
The MPC750 does not support either of the two floating-point imprecise modes supported
by the PowerPC architecture. Unless exceptions are disabled (MSR[FEO]
=
MSR[FEl]
=
0), all floating-point exceptions are treated as precise.
4-18
MPC750 RISC Microprocessor User's Manual
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