Table of Contents
Advertisement
Paragraph
Number
6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.1.3
6.7
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.3.1
7.2.1.3.2
7.2.2
7.2.2.1
7.2.2.1.1
7.2.2.1.2
7.2.3
7.2.3.1
7.2.3.1.1
7.2.3.1.2
7.2.3.2
7.2.3.2.1
7.2.3.2.2
7.2.4
7.2.4.1
7.2.4.1.1
7.2.4.1.2
7.2.4.2
7.2.4.3
7.2.4.3.1
7.2.4.3.2
7.2.4.4
7.2.4.5
7.2.4.6
7.2.4.6.1
7.2.4.6.2
x
CONTENTS
Title
Page
Number
Instruction Scheduling Guidelines ...................................................................... 6-29
Branch, Dispatch, and Completion Unit Resource Requirements ................. 6-29
Branch Resolution Resource Requirements ............................................... 6-30
Dispatch Unit Resource Requirements ....................................................... 6-30
Completion Unit Resource Requirements .................................................. 6-30
Instruction Latency Summary ............................................................................ 6-31
Chapter 7
Signal Configuration ......................... , ................................................................... 7-3
Signal Descriptions ............................................................................................... 7-4
Address Bus Arbitration Signals ...................................................................... 7-4
Bus Request (BR)-Output .......................................................................... 7-4
Bus Grant (BG)-Input ................................................................................ 7-4
Address Bus Busy (ABB) ............................................................................. 7-5
Address Bus Busy (ABB)-Output... ....................................................... 7-5
Address Bus Busy (ABB)-Input ............................................................ 7-5
Address Transfer Start Signals ......................................................................... 7-6
Transfer Start (TS) ........................................................................................ 7-6
Transfer Start (TS)-Output. .................................................................... 7-6
Transfer Start (TS)-Input ....................................................................... 7-6
Address Transfer Signals .................................................................................. 7-6
Address Bus (A[0-31]) ................................................................................ 7-7
Address Bus (A[0-31])-Output ............................................................. 7-7
Address Bus (A[0-31])-Input ................................................................ 7-7
Address Bus Parity (AP[0-3]) ...................................................................... 7-7
Address Bus Parity (AP[0-3])-Output .................................................. 7-7
Address Bus Parity (AP[0-3])-Input ..................................................... 7-8
Address Transfer Attribute Signals .................................................................. 7-8
Transfer Type (TT[O-4]) .............................................................................. 7-8
Transfer Type (TT[O-4])-Output ........................................................... 7-8
Transfer Type (TT[O-4])-Input. ............................................................. 7-8
Transfer Size (TSIZ[0-2])-Output... ........................................................ 7-11
Transfer Burst (TBST) ................................................................................ 7-12
Transfer Burst (TBST)-Output ............................................................ 7 -12
Transfer Burst (TBST)-Input ............................................................... 7-12
Cache Inhibit (CI)-Output ....................................................................... 7-12
Write-Through (WT)-Output... ................................................................ 7-13
Global (GBL) .............................................................................................. 7-13
Global (GBL)-Output .......................................................................... 7-13
Global (GBL)-Input ............................................................................. 7-13
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
