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9.1.6 L2 Clock Configuration
The MPC750 provides a programmable clock for the L2 external synchronous data RAM.
The clock frequency for the external SRAM is provided by dividing the MPC750's internal
clock by ratios of 1, 1.5,2,2.5, or 3, programmed through the L2CR[CLK] bits. The L2
clock is phase-adjusted to synchronize the clocking of the latches in the MPC750's L2
cache interface with the clocking of the external SRAM by means of an on-chip delay-
locked loop (DLL).
The ratio selected for the L2 clock is dependent on the frequency supported by the external
SRAMs, the MPC750's internal frequency of operation, and the range of phase adjustment
supported by the L2 DLL. Refer to the MPC750 hardware specifications for additional
information about L2 clock configuration.
9.1.7 L2 Cache SRAMTiming Examples
This section describes the signal timing for the three types of SRAM (flow-through burst
SRAM, pipelined burst SRAM, and late-write SRAM) supported by the MPC750's L2
cache interface. The timing diagrams illustrate the best case logical (ideal, non AC-timing
accurate) interface operations. For proper interface operation, the designer must select
SRAMs that support the signal sequencing illustrated in the timing diagrams. Designers
should also note that during burst transfers into and out of the L2 cache SRAM array, an
address is generated by the MPC750 for each data beat.
The SRAM selected for a system design is usually a function of desired system
performance, L2 bus frequency, and SRAM unit cost. The following sections describe the
operation of the three SRAM types supported by the MPC750, and the design trade-offs
associated with each.
9.1.7.1 Flow-Through Burst SRAM
Flow-through burst SRAMs operate by clocking in the address, and driving the data directly
to the bus from the SRAM memory array. This behavior allows the flow-through burst
SRAMs to provide initial read data one cycle sooner than pipelined burst SRAMs, but the
flow-through burst SRAM frequencies available may only support the slowest L2 bus
frequencies. The MPC750 supports flow-through burst SRAM at L2 clock ratios of +2,
+2.5, and +3.
Chapter 9. L2 Cache Interface Operation
9-9
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