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Note that setting MSR[EE] masks not only the architecture-defined external
interrupt and decrementer exceptions but also the MPC750-specific system
management, performance monitor, and thermal management exceptions.
- Processor version register (PVR). This register is a read-only register that
identifies the version (model) and revision level of the PowerPC processor.
For more information, see "Processor Version Register (PVR)," in Chapter 2,
"PowerPC Register Set," of The Programming Environments Manual.
Implementation Note-The processor version number is Ox0008 for the
MPC750. The processor revision level starts at OxO I 00 and is updated for each
silicon revision.
-
Memory management registers
Block-address translation (BAT) registers. The PowerPC OEA includes an
array of block address translation registers that can be used to specify four
blocks of instruction space and four blocks of data space. The BAT registers
are implemented in pairs-four pairs of instruction BATs (IBATOU-IBAT3U
and IBATOL-IBAT3L) and four pairs of data BATs (DBATOU-DBAT3U and
DBATOL-DBAT3L). Figure 2-1 lists the SPR numbers for the BAT registers.
For more information, see "BAT Registers," in Chapter 2, "PowerPC Register
Set," of The Programming Environments Manual. Because BAT upper and
lower words are loaded separately, software must ensure that BAT translations
are correct during the time that both BAT entries are being loaded.
The MPC7 50 implements the G bit in the IBAT registers; however, attempting
to execute code from an IBAT area with G
=
1 causes an lSI exception. This
complies with the revision of the architecture described in The Programming
Environments Manual.
- SDRI. The SDRI register specifies the page table base address used in
virtual-to-physical address translation. See "SDRl," in Chapter 2, "PowerPC
Register Set," of The Programming Environments Manual."
- Segment registers (SR). The PowerPC OEA defines sixteen 32-bit segment
registers (SRO-SRI5). Note that the SRs are implemented on 32-bit
implementations only. The fields in the segment register are interpreted
differently depending on the value of bit O. See "Segment Registers," in
Chapter 2, "PowerPC Register Set," of The Programming Environments
Manual for more information.
Note that the MPC750 implements separate memory management units
(MMUs) for instruction and data. It associates the architecture-defined SRs
with the data MMU (DMMU).
It
reflects the values of the SRs in separate,
so-called 'shadow' segment registers in the instruction MMU (IMMU).
Chapter 2. MPC750 Processor Programming Model
2-5
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