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Table 8-3. Aligned Data Transfers (Continued)
Data Bus Byte Lane(s)
Transfer Size
TSIZO
TSIZ1
TSIZ2
A[29-31]
0
1
2
3
4
5
6
Half word
0
1
0
000
..,j
..,j
-
-
-
-
-
0
1
0
010
-
-
..,j
..,j
-
-
-
0
1
0
100
-
-
-
-
..,j
..,j
-
0
1
0
110
-
-
-
-
-
-
..,j
Word
1
0
0
000
..,j
..,j
..,j
..,j
-
-
-
1
0
0
100
-
-
-
-
..,j
..,j
..,j
Double word
0
0
0
000
..,j
..,j
..,j
..,j
..,j
..,j
..,j
Notes: These entries indicate the byte portions of the requested operand that are read or written during
that bus transaction.
These entries are not required and are ignored during read transactions and are driven with unde-
fined data during all write transactions.
'
7
-
-
-
..,j
-
..,j
..,j
The MPC750 supports misaligned memory operations, although their use may
substantially degrade performance. Misaligned memory transfers address memory that is
not aligned to the size of the data being transferred (such as, a word read of an odd byte
address). Although most of these operations hit in the primary cache (or generate burst
memory operations if they miss), the MPC750 interface supports misaligned transfers
within a word (32-bit aligned) boundary, as shown in Table 8-4. Note that the 4-byte
transfer in Table 8-4 is only one example of misalignment. As long as the attempted transfer
does not cross a word boundary, the MPC750 can transfer the data on the misaligned
address (for example, a half-word read from an odd byte-aligned address). An attempt to
address data that crosses a word boundary requires two bus transfers to access the data.
Due to the performance degradations associated with misaligned memory operations, they
are best avoided. In addition to the double-word straddle boundary condition, the address
translation logic can generate substantial exception overhead when the load/store multiple
and load/store string instructions access misaligned data. It is strongly recommended that
software attempt to align data where possible.
8-16
MPC750 RISC Microprocessor User's Manual
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