Motorola MPC750 User Manual page 271

Table 6-4. System Register Instructions (Continued)
Mnemonic Primary Extended Unit Cycles Serialization
mtspr (not liD BATs)
31 467 SRU 2 Execution
mtsr 31 210
SRU
2 Execution
mtsrin 31 242 SRU 2 Execution
mttb 31 467 SRU 1 Execution
rfi 19 50 SRU 2 Completion, refetch
sc 17
- -1
SRU 2 Completion, refetch
sync
31 598 SRU 3
1
-
tlbsync
2
31
566
- -
Notes:
1
This assumes no pending stores in the store queue. If there are, the sync completes after they complete to memory.
If broadcast is enabled on the 60x bus, sync completes only after a successful broadcast.
2
tlbsync is dispatched only to the completion buffer (not to any execution unit) and is marked finished as it is
dispatched. Upon retirement, it waits for an external TLBISYNC signal to be asserted. In most systems ""T"LB"' I "' S "Y"' N ""C
is always asserted so the instruction is a no-op.
Table 6-5 lists condition register logical instruction latencies.
Table 6-5. Condition Register Logical Instructions
Mnemonic Primary Extended Unit Cycles Serialization
crand 19 257 SRU 1 Execution
crandc 19 129 SRU 1 Execution
creqv 19 289 SRU 1 Execution
crnand 19 225 SRU 1 Execution
crnor 19 33 SRU 1 Execution
cror 19 449 SRU 1
Execution
crorc 19 417 SRU 1 Execution
crxor 19 193 SRU 1 Execution
mcrf
19 0 SRU 1 Execution
mcrxr 31 512 SRU
1
Execution
mfcr 31 19 SRU 1 Execution
mtcrf 31
144 SRU 1
Execution
Table 6-6 shows integer instruction latencies. Note that the lUI executes all integer
arithmetic instructions-multiply, divide, shift, rotate, add, subtract, and compare. The IU2
executes all integer instructions except multiply and divide (that is, shift, rotate, add,
subtract, and compare).
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