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Figure 6-4 shows the paths taken by instructions.
Fetch
(Maximum four instructions per clock cycle)
Instruction Queue
~~~§l:~~§l:~~§l:~~§l:~¥\§l:~¥\~~
(In program order)
r--~------------------
I
I
Completion Queue
Assignment
Reservation
Stations
1------1
I
I
LSU
Dispatch
(Maximum 2 instructions per clock cycle; 1 instruction per unit:
IU1
IU2
SRU
Complete (Retire)
Figure 6-4. Instruction Flow Diagram
6-10
MPC750 RISC Microprocessor User's Manual
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