Motorola MPC750 User Manual page 251

Instruction
Oueue
o
2 3 4 5 6 7 8 9 10 11
I I I
Foadd , . . ,
Fetch (in 10)
In dispatch entry (100/101)
I
---
- Execute
pfadd
I
2add
I . . , :
I I I I I I
I
3fadd
- -
Complete (In CO)
In retirement entry (COO/C01)
I
I
F7fadd
I I _ . , _ _
,i
3
5
2 4
1
3 7
0
2 6
bOO
8 add
]
9 add
I
I
10add
I
11 add
I
e,"
I
12fadd
I
12
11 11
10 10 12
9 9
11
8 8 10
7 7
9
..
:
I I I
~'I
I . .
I . _ . _ "
I
13add
I I , . . :
] 14fadd]
p ' _
(18)
(17)
14 (16) (16) (18)
13 (15) (15) (17)
12 14 14 (16)
11
13
13 (15)
Completion
Oueue
12 12 14
o
3
2
1
o
6
3
2
6
3
2
10
8 9
7 8
6
7
3 6
11 11
10 10
9 9
8 8
7 7
Figure 6-5. Instruction Timing-Cache Hit
13
12
11
10
9
The instruction timing for this example is described cycle-by-cycle as follows:
14
13
12
14
11 13
O.
In
cycle 0, instructions 0-3 are fetched from the instruction cache. Instructions 0 and
1 are placed in the two entries in the instruction queue from which they can be
dispatched on the next clock cycle.
6-12
MPC750 RISC Microprocessor User's Manual