Table of Contents
Advertisement
8.5 Timing Examples
This section shows timing diagrams for various scenarios. Figure 8-15 illustrates the fastest
single-beat reads possible for the MPC750. This figure shows both minimal latency and
maximum single-beat throughput. By delaying the data bus tenure, the latency increases,
but, because of split-transaction pipelining, the overall throughput is not affected unless the
data bus latency causes the third address tenure to be delayed.
Note that all bidirectional signals are three-stated between bus tenures.
8-28
I
1
2
3
4
5
6
7
I
8
9
10
11
12
I
'1--,.-_-,-11
I
'LU
A[Q-31]
~-~~~CP~U~A=>----:--<
CPU A
>---:---<C~C~PU~AC=}-+--+-~
TT[O--4]
~-~=~R~ea~d ~>----+--<
Read
>--t--<C:jR~ea~d=}-+--+-~
T8ST
:
ARTRY:
M,
[ 0 :;0;:;'
o(j;lt'~
[iii! ;:;;(i~';it:;;;ii:\
b:;o;:~:
2,
,;O/;!::
:!?:;i<ii;~
OBB:
LU
LU
LU
0[0-63]
:-1
--:---~0>---T---T--<C!J>---T---+---<~>-~--T--"';
T A
~~: ;fj;iiX~:o;:;"i
);:;0:;;\
ORTRY:
TEA:
I
1
5
6
I
7
8
9
I
10
11
12
Figure 8-15. Fastest Single-Beat Reads
MPC750 RISC Microprocessor User's Manual
Advertisement
Table of Contents
